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ltc2970/ltc2970-1 1 29701fb dual i 2 c power supply monitor and margining controller the ltc ? 2970 is a dual power supply monitor and margining controller with an smbus compatible i 2 c bus interface. a low-drift, on-chip reference and 14-bit ? a/d converter allow precise measurements of supply voltages, load currents or internal die temperature. fault manage- ment allows ? a ? l ? e ? r ? t to be asserted for con? gurable over and under voltage fault conditions. two voltage buffered, 8-bit idacs allow highly accurate programming of dc/dc converter output voltages. the idacs can be con? gured to automatically servo the power supplies to the desired voltages using the adc. the ltc2970-1 adds a tracking feature that can be used to turn multiple power supplies on or off in a controlled manner. the bus address is set to 1 of 9 possible combinations by pin strapping the asel0 and asel1 pins. the ltc2970/ ltc2970-1 are packaged in the 24-lead, 4mm 5mm qfn package. dual power supply voltage servo monitoring supply voltage and current programmable power supplies programmable reference less than 0.5% total unadjusted error 14-bit ? adc with on-chip reference dual, 8-bit idacs with 1x voltage buffers linear, voltage servo adjusts supply voltages by ramping idac outputs up/down i 2 c? bus interface (smbus compatible) extensive, user con? gurable fault monitoring on-chip temperature sensor available in 24-lead 4mm 5mm qfn package dual power supply monitor and controller (one of two channels shown) applicatio s u features descriptio u typical applicatio u , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 8v to 15v out fb 0.1 f 0.1 f 0.1 f i? i+ i 2 c bus smbus compatible load dc/dc converter sgnd 29701 ta01 run/ss in v in 1/2 ltc2970 alert scl sda gpio_0 ref 12v in gnd gnd asel0 asel1 v dd gpio_cfg v in0_bm v in0_bp v in0_ap v out0 i out0 v in0_am () temperature ( c) ?50 error (%) ?0.25 0.25 25 75 29701 ta01b ?0.50 ?25 0 50 0 0.50 100 adc v in = 5v 15 parts mounted on pcb adc total unadjusted error vs temperature
ltc2970/ltc2970-1 2 29701fb supply voltages: v dd ......................................................... C0.3v to 6v 12v in .................................................... C0.3v to 15v digital input/output voltages: asel0, asel1 ............................ C0.3v to v dd + 0.3v sda, scl, gpio_cfg, ? a ? l ? e ? r ? t, gpio_0, gpio_1 .......................... C0.3v to 6v analog voltages: v in0_ap , v in0_am , v in0_bp , v in0_bm , v in1_ap , v in1_am , v in1_bp , v in1_bm , v out0 , v out1 .............. C0.3v to 6v i out0 , i out1 , ref ......................... C0.3v to v dd + 0.3v rgnd .................................................... C0.3v to 0.3v operating temperature range: ltc2970c ................................................ 0c to 70c ltc2970i ............................................. C40c to 85c storage temperature range ...................C 65c to 125c lead temperature (soldering, 10 sec) .................. 300c (notes 1 and 2) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v 12vin = 12v, v dd and ref pins ? oating unless otherwise indicated, c vdd = 100nf and c ref = 100nf. electrical characteristics absolute axi u rati gs w ww u symbol parameter conditions min typ max units power-supply characteristics i v12 12v in supply current v 12vin = 12v, v dd floating 4.24 7.5 ma i dd v dd supply current v dd = 5v, v 12vin = v dd 3.7 5 ma v lko v dd undervoltage lockout v dd ramping-down, v 12vin = v dd 3.7 4.14 4.4 v v dd undervoltage lockout hysteresis 118 mv v dd supply input operating range 4.5 5.75 v regulator output voltage 8v v 12vin 15v, C1ma i vdd 0 4.75 4.95 5.25 v regulator output voltage temperature coef? cient 10 ppm/c regulator output voltage load regulation C1ma i vdd 0 160 ppm/ma regulator line regulation 8v v 12vin 15v, i vdd = 0ma 80 ppm/v regulator output short-circuit current v 12vin = 12v, v dd = 0v C5 C34 C63 ma v 12vin 12v in supply operating range 815v package/order i for atio uu w 8 9 top view ufd package 24-lead (4mm 5mm) plastic qfn 10 11 12 24 23 22 21 20 25 6 5 4 3 2 1 v in0_ap v in0_am v in0_bp v in0_bm v in1_ap v in1_am v in1_bp sda scl alert gpio_0 gpio_1 i out0 i out1 rgnd ref asel0 asel1 gpio_cfg v in1_bm v dd 12v in v out0 v out1 7 14 15 16 17 18 19 13 t jmax = 125c, ja = 37c/w exposed pad (pin 25) is gnd must be soldered to pcb order part number ufd part marking* LTC2970CUFD ltc2970iufd LTC2970CUFD-1 ltc2970iufd-1 2970 2970 29701 29701 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container.
ltc2970/ltc2970-1 3 29701fb the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v 12vin = 12v, v dd and ref pins ? oating unless otherwise indicated, c vdd = 100nf and c ref = 100nf. electrical characteristics symbol parameter conditions min typ max units voltage reference characteristics v ref reference output voltage 1.229 v reference voltage temperature coef? cient 2 ppm/c reference overdrive voltage input range 1 1.5 v adc characteristics n_adc resolution n_adc = 8.192v/16384 500 v/lsb tue_adc total unadjusted error v in = 3v, v in = v in n _xp C v in n _xm (note 3) 0.5 % inl_adc integral nonlinearity (note 4) C1 2 4.5 lsb dnl_adc differential nonlinearity (note 7) 0.5 lsb v in_adc input voltage range 06v v os_adc offset error C1000 C316 1000 v offset error drift 0.19 v/c gain_adc gain error full-scale v in = 6v 0.4 % gain error drift 3 ppm/c t conv_adc conversion time 33.3 ms c in_adc input sampling capacitance 3pf f in_adc input sampling frequency 61.4 khz i leak_adc input leakage current 0v < v in < 6v 0.1 a idac output current characteristics n_i out resolution (guaranteed monotonic) 8 bits inl_i out integral nonlinearity v iout n < v dd C 1.5v 1 lsb dnl_i out differential nonlinearity v iout n < v dd C 1.5v 1 lsb i fs- i out full-scale output current v iout n < v dd C 1.5v, dac code = 'hff C236 C255 C276 a i drift- i out output current drift dac code = 'hff 32 ppm/c i os- i out offset current dac code = 'h00 0.1 a voltage buffered idac output characteristics inl_v out integral nonlinearity r iout n = 10k , no load on v out n (note 5) 0.5 lsb dnl_v out differential nonlinearity r iout n = 10k , no load on v out n (note 5) 0.5 lsb v os- v out offset voltage v os = v out n C v iout n , no load on v out n 1.6 10 mv output voltage drift no load on v out n 0.17 v/c v out load regulation 0.1v < v out n < v dd C 1.5v, i vout n source = 1ma C57 ppm/ma 0.1v < v out n < v dd C 1.5v, i vout n sink = 1ma 100 ppm/ma leakage current v out n high-z, 0v v out n v dd 1 100 na short-circuit current low v out n shorted to gnd C50 ma short-circuit current high v out n shorted to v dd 50 ma
ltc2970/ltc2970-1 4 29701fb the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v 12vin = 12v, v dd and ref pins ? oating unless otherwise indicated, c vdd = 100nf and c ref = 100nf. electrical characteristics symbol parameter conditions min typ max units soft connect comparator characteristics (cmp0, cmp1) v os offset voltage 3 mv temperature sensor characteristics tmp gain 0.25 c/lsb 12v in voltage divider characteristics gain_12v in gain 0.329 0.333 0.335 v/v digital inputs scl, sda, gpio_cfg, gpio_0, gpio_1 v ih input high threshold voltage sda, scl 2.1 v gpio_cfg, gpio_0, gipo_1 1.6 v v il input low threshold voltage sda, scl 1.5 v gpio_cfg, gpio_0, gipo_1 1.0 v v hyst input hysteresis 0.08 v i leak input leakage current 0v v in 6v 1 a c in input capacitance 10 pf three state inputs asel[1:0] v ih_asel input high threshold voltage v dd C 0.5 v v il_asel input low threshold voltage 0.5 v i in,hl high, low input current asel[1:0] = 0, v dd 20 a i in,z high z input current 2 a open drain outputs sda, gpio_cfg, gpio_0, gpio_1, ? a ? l ? e ? r ? t v ol output low voltage i sink = 3ma 0.4 v i oh input leakage current 0v v in 6v 1 a symbol parameter conditions min typ max units i 2 c interface timing characteristics f scl serial clock frequency (note 6) 10 400 khz t low serial clock low period (note 6) 1.3 s t high serial clock high period (note 6) 0.6 s t buf bus free time between stop and start (note 6) 1.3 s t hd,sta start condition hold time (note 6) 600 ns t su,sta start condition setup time (note 6) 600 ns t su,sto stop condition setup time (note 6) 600 ns t hd,dat data hold time (ltc2970 receiving data) data hold time (ltc2970 transmitting data) (note 6) 0 300 900 ns ns t su,dat data setup time (ltc2970 receiving data) (note 6) 100 ns t sp pulse width of spike suppressed (note 6) 98 ns the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c.
ltc2970/ltc2970-1 5 29701fb of the transfer curve. the deviation is measured from the center of the quantization band. note 5: nonlinearity is de? ned from the ? rst code that is greater than or equal to the maximum offset speci? cation to code 255 (full-scale). note 6: maximum capacitive load, c b , for scl and sda is 400pf. data and clock risetime (t r ) and falltime (t f ) are: (20 + 0.1 ? c b )(ns) < t r < 300ns and (20 + 0.1 ? c b )(ns) < t f < 300ns. c b = capacitance of one bus line in pf. scl and sda external pull-up voltage, v io , is 3v < v io < 5.5v. note 7: this speci? cation is guaranteed by design. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. electrical characteristics symbol parameter conditions min typ max units t setup_gpio gpio_0 and gpio_1 setup time gpio_0 and gpio_1 input setup time prior to the 26th rising scl of an io() i 2 c read. these inputs must be valid and stable by this time to be returned in the io() read result. (note 6) 2.5 s t hold_gpio gpio_0 and gpio_1 hold time gpio_0 and gpio_1 input hold time after the 26th rising scl of an io() i 2 c read. these inputs must be held until this amount of time has elapsed to be returned in the io() read result. (note 6) 2.5 s t out_gpio gpio_0 and gpio_1 output time gpio_0 and gpio_1 output delay after the 35th rising scl of an i 2 c write. these outputs will become high impedance or begin driving low by this time. (note 6) 2.5 s internal timers t timeout_smb stuck bus timer the ltc2970 will release the i 2 c bus and terminate the current command if the command is not completed before this amount of time has elapsed. 24 32 39 ms t setup_adc adc channel setup time after selecting a new adc channel, the ltc2970 will wait this amount of time to allow the analog input to settle before beginning an adc conversion. 304 s t timeout_ sync tracking sync failure timer ltc2970-1 only: the ltc2970-1 will abort a pending sync() command if a tracking command is not received before this amount of time has elapsed. 255 ms t hold_track tracking idac disconnect delay ltc2970-1 only: after the tracking algorithm asserts cpio_cfg low, the ltc2970-1 will delay disconnecting the idacs from the power supply feedback nodes by this amount of time. used while tracking power supplies on. 32 ms t setup_track tracking idac disconnect delay ltc2970-1 only: after the tracking algorithm asserts cpio_cfg high, the ltc2970-1 will wait this amount of time before starting to decrement ch n _a_ delay_track[9:0]. used while tracking power supplies off. 32 ms t dec_track tracking idac decrement rate ltc2970-1 only: the ltc2970-1 changes ch n _a_delay_track[9:0] at this rate. 88 s/lsb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise speci? ed. note 3: tue (%) is de? ned as % gain error + (inl ? 500 v/lsb + v os ) ? 100 note 4: integral nonlinearity (inl) is de? ned as the deviation of a code from a straight line passing through the actual endpoints (0v and 6v) v in
ltc2970/ltc2970-1 6 29701fb ti i g diagra w u w 29701 td sda scl start condition t buf t r t su;sto stop condition t hd;sta t su;dat t su;sta repeated start condition t high t hd;dat t sp t hd;sta t low t f t f start condition t r the i 2 c bus speci? cation
ltc2970/ltc2970-1 7 29701fb output code (lsbs) ?2 100000 1,000,000 10,000,000 1 29701 g07 10,000 1000 ?1 0 2 100 10 1 number of readings v in = 0v dac code 0 error (lsbs) 0 0.25 200 29701 g08 ?0.25 ?0.50 50 100 150 250 0.50 channels 0 and 1 shown r iout0 = r iout1 = 10k ? dac code 0 error (lsbs) 0 0.25 200 29701 g09 ?0.25 ?0.50 50 100 150 250 0.50 channels 0 and 1 shown r iout0 = r iout1 = 10k ? temperature ( c) ?50 ?0.175 error (%) ?0.150 ?0.100 ?0.075 ?0.050 50 0.050 29701 g01 ?0.125 0 ?25 75 25 100 ?0.025 0 0.025 based on average of 15 parts assembled on 1/8" thick pcb 1v 1.8v 2.5v 3.3v adc v in = 5v input voltage (v) 0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 35 29701 g02 12 46 error (lsbs) input voltage (v) 0 error (lsbs) ?0.25 0 0.25 3 5 29701 g03 ?0.50 ?0.75 ?1.00 12 4 0.50 0.75 1.00 6 temperature ( c) ?50 ?335 v os ( v) ?330 ?325 ?320 ?315 ?305 ?25 02550 29701 g04 75 100 ?310 frequency at v in (hz) 1 ?100 rejection (db) ?90 ?70 ?60 ?50 0 ?30 10 100 29701 g05 ?80 ?20 ?10 ?40 1000 10000 frequency at v in (hz) 0 ?100 rejection (db) ?80 ?60 ?40 5000 10000 15000 20000 29701 g06 25000 ?20 0 ?90 ?70 ?50 ?30 ?10 30000 adc total unadjusted error vs temperature adc inl adc dnl typical perfor a ce characteristics uw adc zero code center offset voltage vs temperature adc rejection vs frequency at v in adc noise histogram voltage buffered idac inl adc rejection vs frequency at v in voltage buffered idac dnl
ltc2970/ltc2970-1 8 29701fb temperature ( c) ?50 256.2 output current ( a) 256.4 256.6 256.8 257.0 257.4 ?25 02550 75 10 0 257.2 idac code = 'hff r iout = 13k ? temperature ( c) ?50 1.590 offset voltage (mv) 1.595 1.600 1.605 1.610 1.620 ?25 02550 29701 g11 75 100 1.615 idac code = 'h00 current (ma) 0 output voltage (v) 3.496 3.498 3.500 ?8 29701 g12 3.494 3.492 3.490 ?2 ?4 ?6 ?10 25 c ?45 c 90 c v iout = 3.5v current (ma) 0 0.25 0.30 0.35 8 29701 g13 0.20 0.15 246 10 0.10 0.05 0 output voltage (v) 90 c 25 c ?45 c v iout = 0.1v 1 s per division 10mv per division 29701 g14 100k ? series resistance on v out r iout = 10k ? code 'h7f code 'h80 5 s per division 10mv per division 29701 g15 100k ? series resistance on v out r iout = 10k ? code 'h80 connected high-z 10 s per division 10mv per division 29701 g16 100k ? series resistance on v out r iout = 10k ? high-z connected temperature ( c) ?50 ?1.5 error ( c) ?1.0 ?0.5 0 0.5 1.5 ?25 02550 29701 g17 75 100 1.0 temperature ( c) ?50 4.945 4.944 4.943 4.942 4.941 4.940 4.939 4.938 25 75 29701 g18 ?25 0 50 100 v dd (v) v 12vin = 12v i vdd = 0a idac output current vs temperature v out n offset voltage vs temperature voltage buffered idac load regulation sourcing voltage buffered idac load regulation sinking voltage buffered idac transient response to 1lsb dac code change voltage buffered idac soft- connect transient response voltage buffered idac transient response during transition from on state to high-z state temperature sensor error vs temperature v dd regulator output voltage vs temperature typical perfor a ce characteristics uw
ltc2970/ltc2970-1 9 29701fb current (ma) 0 ? v dd (ppm) ?500 ?400 ?300 ?3 ?5 29701 g19 ?600 ?700 ?800 ?1 ?2 ?4 ?200 ?100 0 ?45 c 25 c90 c v 12vin = 12v v 12vin (v) 8 ?500 ? v dd (ppm) ?400 ?200 ?100 0 12 400 29701 g20 ?300 10 9 13 14 10 15 100 200 300 25 c 90 c no load on v dd ?45 c temperature ( c) ?50 ?40 short-circuit current (ma) ?35 ?30 ?25 ?25 0 25 50 29701 g21 75 100 v 12vin = 12v v dd = 0v v dd regulator load regulation v dd regulator line regulation v dd regulator short-circuit current vs temperature typical perfor a ce characteristics uw pi fu ctio s uuu v in0_ap (pin 1): positive ch0_a adc multiplexer input. the output of the differential, 7:1 multiplexer connects to the input of the adc. ch0_a can be con? gured to servo idac0. v in0_am (pin 2): negative ch0_a adc multiplexer input. the output of the differential, 7:1 multiplexer connects to the input of the adc. ch0_a can be con? gured to servo idac0. v in0_bp (pin 3): positive ch0_b adc multiplexer input. the output of the differential, 7:1 multiplexer connects to the input of the adc. ch0_b is a voltage monitor input only. v in0_bm (pin 4): negative ch0_b adc multiplexer input. the output of the differential, 7:1 multiplexer connects to the input of the adc. ch0_b is a voltage monitor input only. v in1_ap (pin 5): positive ch1_a adc multiplexer input. the output of the differential, 7:1 multiplexer connects to the input of the adc. ch1_a can be con? gured to servo idac1. v in1_am (pin 6): negative ch1_a adc multiplexer input. the output of the differential, 7:1 multiplexer connects to the input of the adc. ch1_a can be con? gured to servo idac1. v in1_bp (pin 7): positive ch1_b adc multiplexer input. the output of the differential, 7:1 multiplexer connects to the input of the adc. ch1_b is a voltage monitor input only. v in1_bm (pin 8): negative ch1_b adc multiplexer input. the output of the differential, 7:1 multiplexer connects to the input of the adc. ch1_b is a voltage monitor input only. v dd (pin 9): v dd power supply, voltage monitor input, and internal 5v regulator output. the supply input range is 4.5v to 5.75v. the v dd pin voltage can be connected to the adc through an internal mux. bypass the v dd pin to device ground with a 100nf capacitor (c vdd ). if no 5v input voltage supply is available, ? oat the v dd pin and power the ltc2970 from the 12v in pin. 12v in (pin 10): 12v power supply and voltage monitor input. an internal regulator generates 5v from 12v in . the input range for 12v in is 8v to 15v. bypass this pin with a 100nf capacitor. the regulators output is connected to the v dd pin. the 12v in pin voltage can also be monitored by the adc through a 3:1 attenuator and the internal mux. if no 12v supply input is available, tie the 12v in to the v dd pin and operate from 4.5v to 5.75v. v out0 (pin 11): ch0 voltage output. buffered version of idac0 output voltage.
ltc2970/ltc2970-1 10 29701fb pi fu ctio s uuu v out1 (pin 12): ch1 voltage output. buffered version of idac1 output voltage. i out1 (pin 13): idac1 current output. connect a resistor between this pin and the point-of-load ground for channel 1. the idac sources between 0 and 255a. i out0 (pin 14): idac0 current output. connect a resistor between this pin and the point-of-load ground for channel 0. the idac sources between 0 and 255a. gpio_1 (pin 15): general purpose input or open drain digital output. gpio_1 can be con? gured as the idac fault or faults output, a digital input, or an open-drain digital output. gpio_0 (pin 16): general purpose input or open drain digital output. gpio_0 can be con? gured as the voltage monitor power-good or power-good bar output, a digital input, or a programmable open-drain output. power good is the nor of all instantaneous ov and uv faults; it does not include idac faults. ? a ? l ? e ? r ? t (pin 17): open drain digital output. connect the smbalert signal to this pin. ? a ? l ? e ? r ? t is asserted low when either idac0 or idac1 rails out (optional), or when one of the monitored voltages ventures outside its uv and ov thresholds (also optional). scl (pin 18): serial bus clock input. sda (pin 19): serial bus data input and output. gpio_cfg (pin 20): gpio con? guration digital input and open drain output. pulling gpio_cfg high will cause the gpio_0 and gpio_1 open-drain outputs to automatically assert low after a power-on reset. if gpio_cfg is pulled low, then gpio_0 and gpio_1 do not assert low after power-up. asel1 (pin 21): slave address select bit 1. tie this pin to the v dd pin, ground, or ? oat in order to select the address location (see table 2). asel0 (pin 22): slave address select bit 0. tie this pin to the v dd pin, ground, or ? oat in order to select the address location (see table 2). ref (pin 23): internal reference output or adc reference overdrive input. the voltage at this pin determines the full-scale input voltage of the delta-sigma adc (v full- scale = 6.65 ? v ref , typically). an internal 3.5k resistor decouples the reference output from this pin. bypass this pin to rgnd with a 100nf capacitor (c ref ). rgnd (pin 24): reference ground. connect to device ground. gnd (pin 25): device ground. must be soldered to ground.
ltc2970/ltc2970-1 11 29701fb block diagra w 20 gpio_cfg 17 alert 15 gpio_1 16 gpio_0 21 asel1 22 asel0 19 sda 18 scl 23 ref 24 rgnd 8 v in1_bm 7 v in1_bp 6 v in1_am 5 v in1_ap 4 v in0_bm 3 v in0_bp 2 v in0_am 1 v in0_ap 25 gnd 10 12v in 9 v dd v dd 29701 bd idac0 8 bits 2 14 i out0 11 v out0 18 7 idac1 8 bits 13 i out1 12 v out1 ? + ? + ram por adc_results monitor limits servo targets reference 1.229v (typ) clock generation oscillator 3.5k 20 ? r 2r 6.65x (typ) dac soft connect function servo function monitor function manage fault reporting watch dog tracking control (lt2970-1) servo controller i 2 c bus interface (400khz, smbus compatible) 7:1 mux registers i/o configuration idac0 idac1 adc monitor fault enable instantaneous faults latched faults por por v out v in 5v regulator 12v p 12v m v ddp v ddm tsnsp tsnsm ch0_ap ch0_am ch0_bp ch0_bm ch1_ap ch1_am ch1_bm ch1_bp v dd adc clocks uvlo temp sensor v dd 14-bit delta-sigma a/d ? + ? + ? + 0 a to 255 a 0 a to 255 a cmp0 vbuf0 cmp1 vbuf1
ltc2970/ltc2970-1 12 29701fb table of co te ts u u (for operations sections) 1. ltc2970 operation overview .............................................................................................................................1 4 2. i 2 c serial digital interface .............................................................................................................................. ...15 3. register command set .............................................................................................................................. .........16 4. detailed i 2 c command register descriptions ...................................................................................................17 5. soft connecting the ltc2970 to the power supply feedback node ..................................................................21 6. hard connecting the ltc2970 to the power supply trim pin ............................................................................21 7. programming a previously connected idac ......................................................................................................22 8. disconnecting the ltc2970 from the power supply trim pin ...........................................................................22 9. tracking power supplies overview (ltc2970-1 only) .......................................................................................22 10. tracking power supplies on (ltc2970-1 only) .................................................................................................22 11. tracking power supplies off (ltc2970-1 only) .................................................................................................23 12. continuous power supply voltage servo ...........................................................................................................24 13. one time power supply voltage servo .............................................................................................................25 14. one time power supply voltage servo with repeat on fault ..........................................................................25 15. con? guring adc to monitor input channels and internal temperature sensor ................................................25 16. generating and monitoring instantaneous faults ..............................................................................................26 17. generating and monitoring latched faults ........................................................................................................27 18. general purpose input/output pins ....................................................................................................................28 19. advanced development features .......................................................................................................................28
ltc2970/ltc2970-1 13 29701fb 1. ltc2970 operation overview the ltc2970 is designed to control and monitor two power supplies. the ltc2970s superior accuracy allows it to precisely servo each supplys output voltage over a wide range of operating conditions; increasing accuracy, reducing power requirements and component costs. mar- gining may be performed with equal ease and precision. the monitoring functions allow for increased reliability by alerting a system host about incipient failures before they occur. the seven channel adc may also be used to monitor current, temperature, and the 5v or optional 12v supply. the ltc2970s unique architecture and control algorithm have been especially tailored for power supply manage- ment. the soft connect feature allows the ltc2970 to begin controlling a power supply without perturbing its initial value. the delta-sigma adc architecture was speci? cally chosen to average out power-supply noise and allow the ltc2970 to ignore fast transients. unlike discrete time dacs, the ltc2970s continuous time, voltage buffered idac is ideal for noise sensitive applications. the servo algorithm limits the idac step size to one lsb per iteration in order to minimize power supply transients. the point of load ground reference for the idac outputs minimize errors that would otherwise occur in a power system that experiences ground bounce. by selecting two resistor values, the user can choose the appropriate resolution while providing an important hardware range limit beyond which the supply may not be driven. the servo on fault option allows the ltc2970 to further reduce output voltage disturbances by only stepping the idac when the output voltage drifts outside of a user programmable window. the ltc2970 powers up in a high impedance state and will not interfere with default power supply operation. similarly, powering down the ltc2970 will restore its high impedance state. operatio u all communication with the ltc2970 is performed over an industry standard i 2 c bus. the ltc2970 i 2 c interface also meets all smbus setup times, hold times, and timeout requirements. the alert pin may be used to signal that one or more of the fourteen con? gurable fault limits have been reached. each fault may be individually masked. the i 2 c interface supports word reads, word writes and the smbus alert response address protocol. two general purpose io pins may be used to provide additional fault information or user de? ned system control. powering down the ltc2970 will not interfere with i 2 c operation. the ltc2970-1 enables power supply tracking and se- quencing with the addition of a few external components. a special global address and synchronization command allow multiple ltc2970-1s to track and sequence multiple pairs of power supplies. the ltc2970 can perform the following operations: ? accept all programming commands and report status over the i 2 c or smbus bus. ? command each voltage buffered idac to connect to the corresponding power supplys feedback node through an external resistor using the idac code that most closely approximates the feedback nodes regulation voltage (soft connect). ? command each voltage buffered idac output to connect to the corresponding power supplys feedback node through an external resistor with a user-selected idac code (hard connect). ? change the code of a previously connected idac. ? disconnect each voltage buffered idac output from the power supplys feedback node. ? ltc2970-1 only: track two power supplies up or down. multiple ltc2970-1s can be con? gured to track simul- taneously or in a sequence.
ltc2970/ltc2970-1 14 29701fb operatio u the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the ltc2970 i 2 c interface is smbus compatible; it meets all smbus setup times, hold times and timeout require- ments. the ltc2970 is a receive-only (slave) device. the ltc2970 can signal the host through the smbalert protocol that it wants to talk by asserting alert low. the ltc2970 sup- ports the three i 2 c protocols summarized in table 1. slave address the ltc2970 can respond to one of nine 7-bit addresses. the two slave address select pins (asel1 and asel0) are programmed by the user and determine the slave address, as shown in table 2. the ltc2970 also supports the ara address and a global address that allows multiple ltc2970s to be programmed with the same data simultaneously, as shown in table 3. table 1. supported i 2 c command types read data word: s:adr:w:a:cmd:a:sr:adr:r:a:data:a:data:nack:p write data word: s:adr:w:a:cmd:a:data:a:data:a:p alert response s:ara:r:a:adr:nack:p: ? continuously servo one or both supplies to a pro- grammed voltage. ? perform a one-time servo of one or both supplies to a programmed voltage and hold the servo codes in the controlling idac. ? perform a one time servo of one or both supplies to a programmed voltage and hold the code(s) in the controlling idac(s) until over/under voltage monitor- ing detects a fault, at which point a control bit may be used to allow the ltc2970 to servo back to the initial voltage target. ? select any combination of seven possible adc channels to be monitored by the adc. ? generate instantaneous faults based on user program- mable over-voltage and under-voltage limits and ? xed idac limits. the status of ord voltage limit faults and idac faults may be output over gpio_0 and gpio_1, respectively. ? enable instantaneous faults to set associated latched faults using the fault_en register. the status of ord latched faults may be signalled using alert. ? con? gure the gpio_0 and gpio_1 pins to act as inputs or outputs. 2. i 2 c serial digital interface the ltc2970 communicates with a host (master) using the 2-wire, i 2 c serial bus interface. the timing diagram shows the timing relationship of the signals on the bus.
ltc2970/ltc2970-1 15 29701fb operatio u table 2. ltc2970 address table address[7:0] (r/w = 0) address[7:1] asel1 asel0 8hb8 7h5c l l 8hba 7h5d l f 8hbc 7h5e l h 8hbe 7h5f f l 8hd6 7h6b f f 8hd8 7h6c f h 8hda 7h6d h l 8hdc 7h6e h f 8hde 7h6f h h table 3. special ltc2970 addresses address[7:0] (r/w = 0) address[7:1] function ara 8h18 7h0c this is the standard alert response address for all smbus devices. this address is independent of the value of the asel1 and asel0 pins. global 8hb6 7h5b this a global address to which all ltc2970s will respond. this address is independent of the value of the asel1 and asel0 pins. 3. registered command set command function description r/w data length command byte value fault() instantaneous fault status for all channels read only 16 bits h00 fault_en() enable for all latched faults and servo on fault read/write 16 bits h08 fault_la_index() index to all latched faults read only 16 bits h10 fault_la() latched fault status for all channels read only 16 bits h11 io() io control and status register read/write 16 bits h17 adc_mon() control register for selecting adc channels to monitor read/write 16 bits h18 *sync() control register for synchronizing tracking across multiple devices read/write 16 bits h1f vdd_adc() v ddin adc conversion result register read only 16 bits h28 vdd_ov() v ddin over-voltage monitor control register read/write 16 bits h29 vdd_uv() v ddin under-voltage monitor control register read/write 16 bits h2a v12_adc() 12v in adc conversion result register read only 16 bits h38 v12_ov() 12v in over-voltage monitor control register read/write 16 bits h39 v12_uv() 12v in under-voltage monitor control register read/write 16 bits h3a ch0_a_adc() ch0_a adc conversion result register read only 16 bits h40 ch0_a_ov() ch0_a over-voltage monitor control register read/write 16 bits h41 ch0_a_uv() ch0_a under-voltage monitor control register read/write 16 bits h42 ch0_a_servo() ch0_a voltage servo control register read/write 16 bits h43 ch0_a_idac() ch0_a idac control register read/write 16 bits h44 *ch0_a_idac_track() ch0_a idac track final value register read/write 16 bits h45 *ch0_a_delay_track() ch0_a idac track delay register read/write 16 bits h46 ch0_b_adc() ch0_b adc conversion result register read only 16 bits h48 ch0_b_ov() ch0_b over-voltage monitor control register read/write 16 bits h49 ch0_b_uv() ch0_b under-voltage monitor control register read/write 16 bits h4a ch1_a_adc() ch1_a adc conversion result register read only 16 bits h50 ch1_a_ov() ch1_a over-voltage monitor control register read/write 16 bits h51 ch1_a_uv() ch1_a under-voltage monitor control register read/write 16 bits h52 l: v asel n < v il_asel f: asel n floating h: v asel n > v ih_asel
ltc2970/ltc2970-1 16 29701fb operatio u 4. detailed i 2 c command register descriptions fault: instantaneous fault register C read bit(s) symbol operation b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] fault_ch0_a_ov fault_ch0_a_uv fault_ch0_a_idac fault_ch0_b_ov fault_ch0_b_uv fault_ch1_a_ov fault_ch1_a_uv fault_ch1_a_idac fault_ch1_b_ov fault_ch1_b_uv fault_vdd_ov fault_vdd_uv fault_v12_ov fault_v12_uv 0 = the associated channel is clear of instantaneous faults. 1 = the associated channel has an instantaneous fault. the reported faults are instantaneous and not latched. when used in conjunction with latched faults they may indicate faults that are transient in nature. b[15:14] reserved always returns 0 fault_en: fault enabling register C read/write bit(s) symbol operation b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] fault_en_ch0_a_ov fault_en_ch0_a_uv fault_en_ch0_a_idac fault_en_ch0_b_ov fault_en_ch0_b_uv fault_en_ch1_a_ov fault_en_ch1_a_uv fault_en_ch1_a_idac fault_en_ch1_b_ov fault_en_ch1_b_uv fault_en_vdd_ov fault_en_vdd_uv fault_en_v12_ov fault_en_v12_uv 0 = the associated bit in the fault_la register will always be 0. (default) 1 = instantaneous faults reported in the fault register will set associated bit in the fault_la register. b[14] fault_en_ch0_a_servo 0 = do not re-servo ch0_a in response to instantaneous ov or uv fault. 1 = repeat a one time servo of ch0_a in response to instantaneous ov or uv fault. ch0_a must have servo operation enabled with ch0_a_idac_ servo_repeat set low, and adc_mon_ ch0_a set high. b[15] fault_en_ch1_a_servo 0 = do not re-servo ch1_a in response to instantaneous ov or uv fault. 1 = repeat a one time servo of ch1_a in response to instantaneous ov or uv fault. ch1_a must have servo operation enabled with idac_ch1_a_ servo_repeat set low, and adc_mon_ ch1_a set high. 3. registered command set (cont.) command function description r/w data length command byte value ch1_a_servo() ch1_a voltage servo control register read/write 16 bits h53 ch1_a_idac() ch1_a idac control register read/write 16 bits h54 *ch1_a_idac_track() ch1_a idac track control register read/write 16 bits h55 *ch1_a_delay_track() ch1_a idac track delay register read/write 16 bits h56 ch1_b_adc() ch1_b adc conversion result register read only 16 bits h58 ch1_b_ov() ch1_b over-voltage monitor control register read/write 16 bits h59 ch1_b_uv() ch1_b under-voltage monitor control register read/write 16 bits h5a temp_adc() temperature adc conversion result register read/write 16 bits h68 reserved() all other commands are reserved for future expansion and should not be written or read. read/write 16 bits hxx *ltc2970-1 only. ltc2970 will not acknowledge these commands.
ltc2970/ltc2970-1 17 29701fb operatio u fault_index: latched fault index register C read bit(s) symbol operation b[0] fault_la_index 0 = all faults indicated by fault_la are clear. 1 = one or more faults indicated by fault_la are set. this register allows a summary of all latched faults to be viewed in a single read without resetting latched faults. b[15:1] reserved always returns 0 fault_la: latched fault register C read bit(s) symbol operation b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] fault_la_ch0_a_ov fault_la_ch0_a_uv fault_la_ch0_a_idac fault_la_ch0_b_ov fault_la_ch0_b_uv fault_la_ch1_a_ov fault_la_ch1_a_uv fault_la_ch1_a_idac fault_la_ch1_b_ov fault_la_ch1_b_uv fault_la_vdd_ov fault_la_vdd_uv fault_la_v12_ov fault_la_v12_uv 0 = the associated channel is clear of faults. 1 = the associated channel has faulted and is enabled. the latched faults are set and held when the associated instantaneous fault channel has faulted with faults enabled. clearing the enable bit for the associated channel in fault_en will immediately clear its corresponding latched fault bit. all latched channel faults are cleared when this register is read. they may be set again if the instantaneous fault condition and fault_en have not changed. b[15:14] reserved always returns 0 io: input/output data and general purpose control register C read/write unless speci? ed otherwise. bit(s) symbol operation b[1:0] io_cfg_0[1:0] io_cfg_0[1:0] is used to con? gure the function of the gpio_0 pin and io(io_gpio_0). 00: io_gpio_0 = gpio_0 = power_good. power_ good asserts high if there are no instantaneous over-voltage or under-voltage faults. 01: io_gpio_0 = gpio_0 = power_good_bar. power_good_bar is the complement of power_good. 10: gpio_0 is a general-purpose open-drain output and mirrors the value written to io_gpio_0 (default). 11: gpio_0 is a general-purpose digital input with io_gpio_0 = gpio_0 b[3:2] io_cfg_1[1:0] io_cfg_1[1:0] is used to con? gure the function of the gpio_1 pin and io(io_gpio_1). 00: io_gpio_1 = gpio_1 = idac_fault. idac_fault asserts if either idac value is faulted (ch n _idac[7:0] = 8h00 or 8hff) 01: io_gpio_1 = gpio_1 = idac_fault_bar. idac_fault_bar is the complement of idac_fault. 10 = gpio_1 is a general-purpose open- drain output and mirrors the value written to io_gpio_1 (default). 11 = gpio_1 is a general-purpose digital input with io_gpio_1 = gpio_1 b[4] io_gpio_0 see io_cfg_0. if the gpio_cfg pin is pulled-high during a power on reset, io_gpio_0 is cleared and the gpio_0 open-drain output will assert low. b[5] io_gpio_1 see io_cfg_1. if the gpio_cfg pin is pulled-high during a power on reset, io_gpio_1 is cleared and the gpio_1 open-drain output will assert low. b[6] io_alertb mirrors the value of the alert pin. read only. b[7] io_alertb_enb 1 = alert pin never asserts (default). 0 = alert pin asserts low when one or more fault_la bits are set. b[8] io_i2c_adc_ wen 1 = special test mode that inhibits adc from writing to adc result register and allows user to update registers over the i 2 c serial interface. 0 = normal operation (default). b[9] io_gpio_cfg read only. gpio_cfg digital input and open- drain output. reading this bit returns the current state of the gpio_cfg pin voltage. b[10] io_track_start writing a 1 to this bit will start tracking all enabled channels. returns a 1 when tracking is pending (ltc2970-1). reserved on ltc2970 and always returns 0. b[15:11] reserved always returns 0 4. detailed i 2 c command register descriptions (cont.)
ltc2970/ltc2970-1 18 29701fb adc_mon: adc monitoring mux control register C read/write bit(s) symbol operation b[0] b[1] b[2] b[3] b[4] b[5] b[6] adc_mon_vdd adc_mon_v12 adc_mon_ch0_a adc_mon_ch0_b adc_mon_ch1_a adc_mon_ch1_b adc_mon_temp 0 = adc will not convert associated channel. (default) 1 = adc will continuously convert associated channel. b[15:7] reserved always returns 0 sync: tracking synchronization control register C read/write ltc2970-1 only bit(s) symbol operation b[0] sync_track write 0 = do not synchronize. 1 = synchronize all tracking enabled registers to the same starting point. read 0 = the ltc2970-1 is not synchronized for tracking (default). 1 = the ltc2970-1 is synchronized for tracking. use of the global address will allow the synchronization status of multiple ltc2970-1s to be veri? ed in a single read; since a one can only be returned if all ltc2970-1s are synchronized. the io_track_start command may then be issued with the same global address to begin synchronized tracking across multiple ics. b[15:1] reserved always returns 0 operatio u vdd_adc, v12_adc, ch0_a_adc, ch0_b_adc, ch1_a_adc, ch1_b_adc, and temp_adc: adc conversion result registers C read only unless speci? ed otherwise bit(s) symbol operation b[14:0] vdd_adc[14:0] v12_adc[14:0] ch0_a_adc[14:0] ch0_b_adc[14:0] ch1_a_adc[14:0] ch1_b_adc[14:0] temp_adc[14:0] measured data from adc conversion. 'h4000 corresponds to negative full- scale input voltage. 'h0000 corresponds to 0v. 'h3fff corresponds to full-scale input voltage. 2s complement format, b[14] = sign. read/write when io_i2c_adc_wen = 1. default value is unde? ned. b[15] vdd_adc_new v12_adc_new ch0_a_adc_new ch0_b_adc_new ch1_a_adc_new ch1_b_adc_new temp_adc_new 1 = the adc has updated the associated result register since the last time the data was read. 0 = previously read data. (default) vdd_ov, v12_ov, ch0_a_ov, ch0_b_ov, ch1_a_ov, ch1_b_ ov: over voltage limit registers C read/write bit(s) symbol operation b[14:0] vdd_ov[14:0] v12_ov[14:0] ch0_a_ov[14:0] ch0_b_ov[14:0] ch1_a_ov[14:0] ch1_b_ov[14:0] adc over-voltage threshold limit. the associated instantaneous over voltage fault is asserted if the channels adc result is greater than this limit. code 'h3fff disables ov threshold detect feature for that channel. 2s complement format, b[14] = sign. default value is unde? ned. b[15] reserved always returns 0 vdd_uv, v12_uv, ch0_a_uv, ch0_b_uv, ch1_a_uv, ch1_b_ uv: under voltage limit registers C read/write bit(s) symbol operation b[14:0] vdd_uv[14:0] v12_uv[14:0] ch0_a_uv[14:0] ch0_b_uv[14:0] ch1_a_uv[14:0] ch1_b_uv[14:0] adc under-voltage threshold limit. the associated instantaneous under voltage fault is asserted if the channels adc result is greater than this limit. code 'h4000 disables uv threshold detect feature for that channel. 2s complement format, b[14] = sign. default value is unde? ned. b[15] reserved always returns 0 4. detailed i 2 c command register descriptions (cont.)
ltc2970/ltc2970-1 19 29701fb operatio u ch0_a_servo, ch1_a_servo: voltage servo control registers C read/write bit(s) symbol operation b[14:0] ch0_a_servo[14:0] ch1_a_servo[14:0] during servo operation ch n _a_idac[7:0] output current is stepped to force ch n _a_adc[14:0] code to equal target code stored in ch n _a_servo[14:0]. 2s complement format, b[14] = sign default value is unde? ned. b[15] ch0_a_servo_en ch1_a_servo_en 0 = ch n _a servo disabled (default). 1 = ch n _a servo enabled. ch0_a_idac, ch1_a_idac: idac control/data registers C read/write bit(s) symbol operation b[7:0] ch0_a_idac[7:0] ch1_a_idac[7:0] ch n _a idac data value. b[8] ch0_a_idac_en ch1_a_idac_en 0 = v out n output tri-stated. 1 = v out n output enabled. there are two ways to enable v out n . 1) when ch n _a_idac_en is set high with ch n _a_idac_con low, the ltc2970 will perform a soft connect. during a soft connect, the v out n voltage buffer output will not be connected to the v out n pin until the internal algorithm has servod the voltage at the idac n pin to match the v out n pin voltage. resolution is one ch n _a_idac lsb. 2) when ch n _a_idac_en is enabled with ch n _a_idac_con high, the ltc2970 will perform a hard connect. the v out n voltage buffer will be immediately connected to the v out n pin. b[9] ch0_a_idac_con ch1_a_idac_con 0 = v out n is not enabled or has been enabled but is not yet connected to the output of the ch n voltage buffer. (default) 1 = v out n is enabled and has been connected to the output of the ch n voltage buffer. see ch n _a_idac_en for additional information. b[10] ch0_a_idac_pol ch1_a_idac_pol 0 = use this setting when increasing v outn causes (vin n _ap-vin n _am) to decrease. inverting con? guration common to dc/dc converters with external feedback networks. 1 = use this setting when increasing v out n causes (vin n _ap-vin n _am) to increase. non-inverting con? guration common to dc/dc converters with trim pins. b[11] ch0_a_idac_servo_repeat ch1_a_idac_servo_repeat 0 = during servo operation, servo ch n _a until the measured result is stable and matches the target code. 1 = during servo operation, continuously servo ch n _a to the target code. b[15:12] reserved always returns 0 ch0_a_idac_track and ch1_a_idac_track: idac tracking data and control registers C read/write ltc2970-1 only bit(s) symbol operation b[7:0] ch0_a_idac_ track[7:0] ch1_a_idac_ track[7:0] final target value for of ch n _a_ idac[7:0]. during tracking, ch n _a_ idac[7:0] is incremented/decremented by 1 until it is equal to this value. b[8] ch0_a_idac_track_en ch1_a_idac_track_en 0 = inhibit tracking of ch n _a_idac[7:0]. 1 = enable tracking of ch n _a_idac[7:0] b[15:9] reserved always returns 0 ch0_a_delay_track and ch1_a_delay_track: idac tracking delay register C read/write ltc2970-1 only bit(s) symbol operation b[9:0] ch0_a_delay_track[9:0] ch1_a_delay_track[9:0] delay used to synchronize or offset tracking events. b[1510] reserved always returns 0 4. detailed i 2 c command register descriptions (cont.)
ltc2970/ltc2970-1 20 29701fb operatio u 5. soft connecting the ltc2970 to the power supply feedback node the soft connect feature allows the ltc2970 to connect to the power supplys feedback node with minimal disturbance to the supplys output voltage. this is accomplished by comparing the buffered voltage of i out n to the voltage at v out n and incrementing or decrementing ch n _a_idac[7:0] until the comparator output (comp n ) changes. the value of ch n _a_idac[7:0] when the comparator transitions is the appropriate value for a soft connect. the voltage buffer output is only connected to v out n if the idac reaches this soft connect value without generating an instantaneous idac fault (fault_ch n _a_idac). soft-connect procedure: determine the appropriate polarity for ch n _a_idac_pol. select ch n _a_idac_pol = 1 if incrementing v out n causes differential voltage (vin n _ap C vin n _am) to increase. when properly programmed, lowering the value in ch n _ a_idac[7:0] will always cause the output of the controlled power supply to decrease. ensure that the channels idac is not currently enabled for connection, i.e., the ch n _a_idac_en bit must be 0. update ch n _a_idac() with ch n _a_idac_pol, ch n _a_idac_ con = 0, ch n _a_idac_en = 1, and ch n _a_idac[7:0] = 0x80. the value programmed into ch n _a_idac[7:0] is ignored and ch n _a_idac[7:0] is initially set to 8h80. the ltc2970 will now ramp ch n _a_idac[7:0] while moni- toring the output of the soft connect comparator. if the soft connect comparator trips, the ltc2970 will connect the output of v buf n to v out n and set ch n _a_idac_con high. if the soft connect comparator does not trip before the idac value reaches h00 or hff, then the soft connection will fail, an idac fault will be indicated (fault_ch n _a_idac), and ch n _a_idac_con will remain low. soft-connect rules: when both channels are requesting a soft connect, chan- nel 0 has priority. soft connect requests will be ignored and the user will not be able to change ch n _a_idac_pol or ch n _a_idac[7:0] if the ltc2970 is servicing a previously issued soft connect on that channel or the previously issued soft connect failed with an idac fault (fault_ch n _a_idac = 1). recall that the ch n _a_idac_en bit must initially have been set to 0. ltc2970-1 only: soft connect requests will be ignored and the user will not be able to change ch n _a_idac_pol or ch n _a_idac[7:0] if gpio_cfg is high and either gpio_0 or gpio_1 are high. ltc2970-1 only: soft connect requests will be ignored and the user will not be able to change the ch n _a_idac_pol bit if there is a pending tracking operation. 6. hard connecting the ltc2970 to the power supply trim pin the hard connect feature allows the ltc2970 to bypass the soft connect algorithm and connect directly to the power supplys feedback node using the value programmed into ch n _a_idac[7:0]. this feature is useful for systems that have calculated or measured an acceptable voltage at which to connect the idacs buffered voltage v buf n to v out n . hard connect procedure: determine the appropriate polarity for ch n _a_idac_pol. select ch n _a_idac_pol = 1 if incrementing v out n causes (vin n _ap C vin n _ap) to increase. when properly pro- grammed, lowering the value in the idac will always cause the output of the controlled power supply to decrease. determine the value for ch n _a_idac[7:0]. the values h00 or hff are allowed, but they will trip the idacs fault bit (fault_ch n _a_idac = 1). when the idac is already connected, the value ch n _a_ idac[7:0] and ch n _a_idac_pol will be programmed into the idac provided all other conditions are met. see program- ming a previously connected current dac for details update ch n _a_idac() with ch n _a_idac_pol, ch n _a_idac_ con = 1, ch n _a_idac_en = 1, and ch n _a_idac[7:0]. hard connect rules: hard connect requests will be ignored and the user will not be able to change ch n _a_idac_pol, ch n _a_idac_con or ch n _a_idac[7:0] if the ltc2970 is servicing a previously issued soft connect on that channel or the previously issued
ltc2970/ltc2970-1 21 29701fb operatio u soft connect failed with an idac fault (fault_ch n _a_idac = 1). recall that a new hard connection requires the previous value of ch n _a_idac_en = 0. ltc2970-1 only: hard connect requests will be ignored and the user will not be able to change ch n _a_idac_pol, ch n _a_idac_con or ch n _a_idac[7:0] if gpio_cfg is high and either gpio_0 or gpio_1 are high. ltc2970-1 only: hard connect requests will be ignored and the user will not be able to change ch n _a_idac_pol, ch n _a_ idac_con or ch n _a_idac[7:0] if there is a pending tracking operation. 7. programming a previously connected idac the ltc2970 idacs may be programmed after they have been connected with a soft connect or a hard connect provided a servo operation is not enabled on the associ- ated channel. procedure: determine the value for ch n _a_idac[7:0]. the values h00 or hff are allowed, but will trip the idacs fault bit (fault_ch n _a_idac = 1). verify that the idac is already connected, and that ch n _a_idac_con is high. ensure that servo mode is not enabled for the channel being programmed. ch n _a_servo_en must be low. this requirement prevents the user from interfering with a previously requested servo operation. update the ch n _a_idac() register with ch n _a_idac_pol, ch n _a_idac_con = 1, ch n _a_idac_en = 1, and ch n _a_ idac[7:0]. note: care should be taken to preserve the current value of the ch n _a_idac_pol bit, since the ltc2970 does not prevent the user from changing this value when writing to the idac control registers. rules: setting ch n _a_idac_con to zero will not disconnect the dac unless ch n _a_idac_en is also set low. all hard connect rules apply. 8. disconnecting the ltc2970 from the power supply trim pin v out n can be placed in a high impedance state simply by clearing the ch n _a_idac_en bit. in order to minimize the resulting disturbance to the power supply voltage, the idac code should not be changed from its current value when clearing the ch n _a_idac_en bit. this is not an issue if the channels associated servo_en bit is high. disconnect procedure: update ch n _idac() with ch n _a_idac_en set low. the ltc2970 will immediately disconnect the buffered i out n from v out n . disconnect rules: clearing ch n _a_idac_con with ch n _a_idac_en high will not disconnect the idac. only setting ch n _a_idac_en low will clear ch n _a_idac_con. ltc2970-1 only: ch n _a_idac_en may not be changed if the feedback node connection is con? gured for tracking. tracking is enabled when gpio_cfg is high and either gpio_0 or gpio_1 are high. 9. tracking power supplies overview (ltc2970-1 only) the ltc2970-1 tracking feature allows the i 2 c interface to initiate a controlled power up or power down of two or more supplies (figure 2 shows a typical ltc2970-1 application circuit). multiple ltc2970-1s with different addresses may be simultaneously programmed using the ltc2970 group address and the sync() command. tracking is enabled when gpio_cfg is pulled high and either gpio_0 or gpio_1 are high. 10. tracking power supplies on (ltc2970-1 only) the ltc2970-1 tracking feature allows the i 2 c to initiate a controlled power up of two or more supplies. procedure: this procedure describes all the steps neces- sary to track up two or more power supplies. steps that require i 2 c interaction are pre? xed with the required i 2 c command function. power-up the ltc2970-1 with gpio_cfg pulled high.
ltc2970/ltc2970-1 22 29701fb operatio u this causes open-drain outputs gpio_1 and gpio_0 to automatically pull the power supplies run/soft-start pins to ground. ch n _a_idac(): hard connect ch n _a_idac[7:0] with a value that forces the power supplies off when gpio_cfg = 1. verify that ch n _a_idac_pol is at the appropriate value. ch n _a_idac_track(): set ch n _a_idac_track_en = 1, and set the ch n _a_idac_track[7:0] target value to the code that causes v out n to most closely approximate the corresponding power supplys feedback node voltage when it is in regulation. ch n _a_delay_track(): set the value by which the incrementing of idac n should be delayed with respect to the start of tracking event. this controls whether the power supplies track up coincidentally or sequentially. io(): release the run/soft-start pins by programming io_gpio_ n = 1. this will enable the power supplies without allowing their outputs to move since these are held off by ch n _a_idac[7:0]. wait until power supplies have had suf- ? cient time to start running before starting tracking. sync(): optional command that allows multiple ltc2970- 1s to be synchronized for tracking. writing sync_track = 1 will allow the ltc2970-1 to ? nish its current adc conversion before having it wait to receive io_track_start = 1. the ltc2970-1 will timeout this wait command after t timeout_sync . reading back sync_track = 1 using the global address will ensure all ltc2970-1s are synchronized before proceeding with the tracking operation. io(): set io_track_start = 1 and keep the run/soft-start pins enabled. use the global i 2 c address to simultaneously track up power supplies across multiple ltc2970-1s. ltc2970-1 response: for each tracking enabled channel, the ltc2970-1 will decrement the ch n _a_delay_track counter at a rate of t dec_track . as soon as a channels tracking counter reaches zero, the ltc2970-1 will begin stepping the value of ch n _a_idac[7:0] by one count until the ? nal value of ch n _a_idac_track[7:0] is reached, at which point ch n _a_idac_track_en is de-asserted. when the ? nal value is reached for all channels, gpio_cfg is asserted low. after a time delay of t hold_track , ch n _a_idac_en is de-asserted. power-up tracking rules: tracking cannot begin if ch n _a_idac_con is not connected. this condition is met when the previous procedure is followed. ch n _a_idac_track_pol, ch n _a_idac_track_en, and ch0_ idac[7:0] updates will be ignored after io(io_track_start) is asserted until tracking is complete or whenever tracking is pending, i.e., gpio_cfg pulled high with either gpio_0 or gpio_1 asserted pulled high. 11. tracking power supplies off (ltc2970-1 only) the ltc2970-1 tracking feature allows the i 2 c to initiate a controlled power down of two or more supplies. procedure: this procedure describes all steps necessary to track down two or more power supplies. steps that require i 2 c interaction are pre? xed with the required i 2 c command function. ch n _idac(): disable the idacs for each tracking enabled channel (ch n _a_idac_en = 0). ensure ch n _a_idac_pol is at the appropriate value. ch n _idac_track(): select the channels to be tracked by setting ch n _a_idac_track_en = 1, and set the target value for each ch n _a_idac_track[7:0] to that which forces the supply off. ch n _a_delay_track(): set the value by which the decrementing of that channels dac should be delayed with respect to the start of the tracking event. this con- trols whether the supplies track down coincidentally or sequentially. sync(): optional command that allows multiple ltc2970- 1s to be synchronized for tracking. writing sync_track = 1 will allow the ltc2970-1 to ? nish its current adc conversion before having it wait to receive io_track_start = 1. the ltc2970-1 will timeout this wait command after t timeout_sync . reading back sync_track = 1 using the global address will ensure all ltc2970s are synchronized before proceeding with the tracking operation. io(): set io_track_start = 1. use the global i 2 c address to simultaneously track down power supplies across multiple ltc2970s.
ltc2970/ltc2970-1 23 29701fb operatio u ltc2970-1 response: each tracking enabled channel is soft connected. the gpio_cfg pin is released allowing it to be pulled high. the ltc2970-1 waits t setup_track to allow gpio_cfg to settle. for each tracking enabled channel, the ch n _a_delay_track counter is decremented at a rate of t dec_track . as soon as a channels tracking counter reaches zero, the ltc2970-1 will begin stepping the value of ch n _a_idac[7:0] by one count until the ? nal value of ch n _a_idac_track[7:0] is reached. the tracking enable bit is then cleared for both channels (ch n _a_idac_track_en = 0). io(): the i 2 c interface may then be used to set gpio_1 and gpio_0 low, disabling the power supplies. power down tracking rules: power down tracking requests will be ignored until the user has disabled the idacs by setting ch n _a_idac_en = 0 for each tracking enabled channel. ch n _a_idac_track_pol, ch n _a_idac_track_en, and ch0_ idac[7:0] updates will be ignored after io(io_track_start) is asserted until tracking is complete and whenever tracking range is con? gured; (gpio_cfg high with either gpio_0 or gpio_1 asserted high). 12. continuous power supply voltage servo the continuous voltage servo feature allows the ltc2970 to servo an external power supply to a programmed value. the voltage of the external supply is monitored over ch n _a_adc and compared to a target value stored in ch n _a_servo. after each conversion, ch n _a_idac is incremented by 1, decremented by 1, or held; whichever brings or keeps the measured voltage closer to the targeted servo value. procedure: follow procedure for hard connecting or soft connecting the ltc2970 to power supply trim pin; when updating ch n _a_idac(), ch n _a_idac_servo_repeat should be as- serted high. the servo channels idac must be enabled before ch n _a_servo_en can be set high. determine the target servo voltage, ch n _a_servo[14:0]. update ch n _a_servo() with ch n _a_servo_en = 1, and ch n _a_servo[14:0]. update ch n _a_idac() with ch n _a_idac_servo_repeat = 1. this step may be skipped if ch n _a_idac_servo_repeat was set high during the soft or hard connect procedure. ltc2970 response: the ltc2970 will continuously in- crement, decrement or hold ch n _a_idac[7:0] in order to match the measured value of (vin n _ap-vin n _am) to ch n _a_servo[14:0]. whenever the ch n _a_servo() register is updated an in- ternal ? ag is cleared indicating that a successful servo has not been completed. this internal ? ag, ch n _a_servo_done, initially causes the adc to operate in an accelerated 12-bit mode. once the channel reaches the servo target, the adc switches back to 14-bit mode for two conversions before asserting ch n _a_servo_done high. in continuous voltage servo mode the ch n _a_servo_done ? ags allow the initial servo target to be reached quickly. during this time, adc conversions for all non-servo chan- nels are temporarily inhibited. rules: the idac associated with the servo channel must be enabled. if ch n _a_idac_en is low the servo enable bit ch n _a_servo_en is always forced low. the idac associated with the servo channel must be con- nected (ch n _a_idac_con = 1). an idac fault may be generated during a continuous servo operation. the ltc2970 will report the fault and continue trying to servo that channel. ltc2970-1 only: there must be no pending tracking commands. a pending tracking command will clear ch n _a_servo_en. ltc2970-1 only: the tracking range must not be enabled; (gpio_cfg high with either gpio_0 or gpio_1 asserted high). an enabled tracking range will clear ch n _a_servo_en low.
ltc2970/ltc2970-1 24 29701fb operatio u 13. one time power supply voltage servo the one time voltage servo feature allows the ltc2970 to servo an external power supply to a programmed value and then stop updating the idac once the target value has been reached. procedure: follow procedure for hard connecting or soft connecting the ltc2970 to power supply trim pin; when updating ch n _a_idac(), ch n _a_idac_servo_repeat should be de- asserted low. the servo channels idac must be enabled before ch n _a_servo_en may be set high. update ch n _a_idac() with ch n _a_idac_servo_repeat = 0. this step may be skipped if ch n _a_idac_servo_repeat was cleared low during the soft or hard connect procedure. update fault_en() with fault_en_ch n _a_servo = 0. this prevents the ltc2970 from reinitiating a servo after an over-voltage or under-voltage fault. determine the target servo voltage, ch n _a_servo[14:0]. update ch n _a_servo() register with ch n _a_servo_en = 1, and ch n _a_servo[14:0]. ltc2970 response: the ltc2970 will increment, decrement or hold ch n _a_idac[7:0] in order to match the measured value of (vin n _ap-vin n _am) to ch n _a_servo[14:0]. the servo procedure will end when the internal ch n _a_servo_ done ? ag is set (see continuous power supply voltage servo). at this point the idac is either programmed to the appropriate servo value or faulted. rules: all continuous power supply voltage servo rules apply. 14. one time power supply voltage servo with repeat on fault the ltc2970 one time voltage servo feature may be modi? ed to allow the ltc2970 to perform an additional power supply servo operation after an under-voltage or over-voltage fault is detected on the servo channel. procedure: follow procedure outlined for one time power supply voltage servo. update fault_en() with fault_en_ch n _a_servo = 1. enable detection of the appropriate instantaneous faults for all servo channels; see generating and monitoring instantaneous faults. ltc2970 response: any time an instantaneous under- voltage or over-voltage fault is detected on the servo channel (fault_ov_a_ch n or fault_uv_a_ch n ), the internal ch n _a_servo_done ? ag for that channel is cleared, and the ltc2970 will perform a complete one time servo. this allows the ltc2970 to precisely restore the power supply to the target servo value, after it has drifted beyond a user de? ned operating window. rules: all continuous power supply voltage servo rules apply. during a permanent under-voltage or over-voltage fault the ltc2970 will continuously try to correct the faulted channel, after each failed attempt all other channels that need monitoring by the adc will be serviced. 15. con? guring adc to monitor input channels and internal temperature sensor the ltc2970 is able to perform adc conversions on any combination of seven different input channels. a channel is converted if its associated adc_mon() bit is set high. refer to table 7 for details. procedure: update adc_mon() with the control bit of each channel that is to be monitored set high. ltc2970 response: all enabled channels will be sequen- tially converted. the result of the most recent conversion may be read from the adc result register. each time a conversion is completed the new data bit associated with the result register is asserted high. the new data bit is
ltc2970/ltc2970-1 25 29701fb operatio u table 7. ltc2970 adc conversion and fault limit registers input channel adc_mon() control bit adc result register (2s complement) ov fault register (2s complement) uv fault register (2s complement) temperature adc_mon_temp temp_adc[14:0] - - vin1_bp-vin1_bm adc_mon_b_ch1 ch1_b_adc[14:0] ch1_b_ov[14:0] ch1_b_uv[14:0] vin1_ap-vin1_am adc_mon_a_ch1 ch1_a_adc[14:0] ch1_a_ov[14:0] ch1_a_uv[14:0] vin0_bp-vin0_bm adc_mon_b_ch0 ch0_b_adc[14:0] ch0_b_ov[14:0] ch0_b_uv[14:0] vin0_ap-vin0_am adc_mon_a_ch0 ch0_a_adc[14:0] ch0_a_ov[14:0] ch0_a_uv[14:0] 12vin adc_mon_v12 v12_adc[14:0] v12_ov[14:0] v12_uv[14:0] vdd adc_mon_vdd vdd_adc[14:0] vdd_ov[14:0] vdd_uv[14:0] reset each time the result register is read. this provides a simple mechanism for supervisory software to determine if a new conversion has been completed since data was last read. rules: the ltc2970 assigns priority to adc conversions of ch1_a_adc and ch0_a_adc when these channels are in their initial fast servo mode. the io() register control bit io_i2c_adc_wen must be low in order for adc conversions to be performed. ltc2970-1 only: adc conversions are suspended during any pending tracking requests. 16. generating and monitoring instantaneous faults the ltc2970 supports fourteen different types of instan- taneous faults. these faults together with the conditions that trigger them are de? ned in table 8. there are six under-voltage faults, six over-voltage faults and two idac limit faults. the fault() command may be used to read the status of all instantaneous fault bits. the io() com- mand may be used to con? gure gpio_0 and gpio_1 to view voltage limit and idac faults respectively. the state of gpio_0 and gpio_1 may be read using io(). table 8. ltc2970 fault reporting bits and conditions condition that generates an instantaneous fault fault() instantaneous fault reporting fault_en() enable for latched fault reporting fault_la() latched fault reporting v12_adc[14:0] < v12_uv[14:0] fault_v12_uv fault_en_v12_uv fault_la_v12_uv v12_adc[14:0] > v12_ov[14:0] fault_v12_ov fault_en_v12_ov fault_la_v12_ov vdd_adc[14:0] < vdd_uv[14:0] fault_vdd_uv fault_en_vdd_uv fault_la_vdd_uv vdd_adc[14:0] > vdd_ov[14:0] fault_vdd_ov fault_en_vdd_ov fault_la_vdd_ov ch1_b_adc[14:0] < ch1_b_uv[14:0] fault_ch1_b_uv fault_en_ch1_b_uv fault_la_ch1_b_uv ch1_b_adc[14:0] > ch1_b_ov[14:0] fault_ch1_b_ov fault_en_ch1_b_ov fault_la_ch1_b_ov idac_a_ch1[7:0] = 8ff or 8h00 fault_ch1_a_idac fault_en_ch1_a_idac fault_la_ch1_a_idac ch1_a_adc[14:0] < ch1_a_uv[14:0] fault_ch1_a_uv fault_en_ch1_a_uv fault_la_ch1_a_uv ch1_a_adc[14:0] > ch1_a_ov[14:0] fault_ch1_a_ov fault_en_ch1_a_ov fault_la_ch1_a_ov ch0_b_adc[14:0] < ch0_b_uv[14:0] fault_ch0_b_uv fault_en_ch0_b_uv fault_la_ch0_b_uv ch0_b_adc[14:0] > ch0_b_ov[14:0] fault_ch0_b_ov fault_en_ch0_b_ov fault_la_ch0_b_ov idac_a_ch0[7:0] = 8ff or 8h00 fault_ch0_a_idac fault_en_ch0_a_idac fault_la_ch0_a_idac ch0_a_adc[14:0] < ch0_a_uv[14:0] fault_ch0_a_uv fault_en_ch0_a_uv fault_la_ch0_a_uv ch0_a_adc[14:0] > ch0_a_ov[14:0] fault_ch0_a_ov fault_en_ch0_a_ov fault_la_ch0_a_ov
ltc2970/ltc2970-1 26 29701fb operatio u procedure: update the over-voltage limit register with the value above which the adc result should generate an over-voltage fault. instantaneous over-voltage faults are updated after each adc conversion. they are asserted high when the adc result is greater than the over-voltage limit. they are cleared if the adc result is less than or equal to the over-voltage limit. setting the over-voltage limit to 14h3fff inhibits instantaneous faults for the associated channel. update the under-voltage limit register with the value below which the adc result should generate an under-voltage fault. instantaneous under-voltage faults are updated after each adc conversion. they are asserted high when the adc result is less than the under-voltage limit. they are cleared if the adc result is greater than or equal to the under-voltage limit. setting the over-voltage limit to 14h4000 inhibits instantaneous faults for the associated channel. update adc_mon() control bits to allow adc conversions on all channels that are to be monitored for over and under voltage limits. instantaneous idac faults are polled after all adc conversions are completed and set when the as- sociated idac registers are at h00 of hff. read fault() to view the value of all instantaneous faults. the io(io_cfg_0) command may be used to con? gure the gpio_0 pin to output the internal power_good ? ag. power_good is asserted high if there are no instantaneous over-voltage or under-voltage faults. io() may be used to read the value of power_good through io_gpio_0. the io(io_cfg_1) command may be used to con? gure the gpio_1 pin to output the internal idac_fault ? ag. idac_fault is asserted high if either idac value is faulted. io() may be used to read the value of idac_fault through io_gpio_1. rules: the over-voltage and under-voltage limits must be initial- ized; they do not have a default value. all over-voltage limits, under-voltage limits and adc re- sults use 2s complement notation with bit position [14] of register [14:0] being used for the sign. instantaneous ch0_a and ch1_a faults may be used to trigger a servo on fault event. over-voltage and under-voltage faults require that the associated adc_mon control bit be asserted high for instantaneous fault detection to be updated. 17. generating and monitoring latched faults the ltc2970 is able to selectively latch instantaneous faults in the latched fault register fault_la. each instantaneous fault has an associated latched fault bit in fault_la and a fault enable bit in fault_en; (see table 8) for details. when an instantaneous fault enable bit is high, any event that sets the instantaneous fault will simultaneously set the latched fault. the latched fault will remain set even if conditions permit the instantaneous fault to be cleared. the latched faults are immediately cleared whenever the associated fault enable bit is cleared. all latched faults are also cleared when the latched fault register is read over fault_la(). the fault_index() command may be read to determine if any latched faults are asserted. reading fault_index() does not clear latched faults. the alert output may also be con? gured to view whether any latched faults are as- serted. procedure: follow procedure for generating instantaneous faults. write fault_en() to enable any combination of latched faults. read fault_index() to determine if any latched faults are asserted without clearing latched faults. read fault_la() to monitor all latched faults. reading fault_la() will clear all latched faults. these will remain clear until the next time the ltc2970 polls and sets an associated instantaneous fault. setting io(io_alert_enb) low will cause alert to be as- serted low whenever any one of the fourteen latched faults is asserted high. the value of the alert pin may also be read through io(alertb).
ltc2970/ltc2970-1 27 29701fb applicatio s i for atio wu u u operatio u rules: see generating and monitoring instantaneous faults. 18. general purpose input/output pins the gpio_0 and gpio_1 may be used to: (1) monitor instantaneous faults (see generating and monitoring instantaneous faults); (2) control switcher run/start pins during tracking (see tracking power supplies overview); or (3) provide general purpose input/output pins. procedure: to program gpio_ n as an open drain output set io_cfg_ n = 2b10. the value written to lo_gpio_ n will be output over gpio_ n . to program gpio_ n as an input set io_cfg_ n = 2b11. the value of gpio_ n may now be read through lo_gpio_ n . rules: the power on reset con? gurations for gpio_0 and gpio_1 are output pins with a value equal to the complement of the gpio_cfg level. 19. advanced development features the internal adc may be disabled with the adc result registers accepting written i 2 c data. this feature allows faults to be generated for diagnostic purposes, without having to generate an actual overvoltage or undervoltage event. procedure: set io(io_i2c_adc_wen) high to enable adc result register writes and disable internal adc updates. rules: io_i2c_adc_wen must be clear for normal operation. margining dc/dc converters with external feedback resistors figure 1 shows a typical application circuit for margining a power supply with an external feedback network. the v in0_ap and v in0_am differential inputs sense the load volt- age directly, and differential inputs v in0_bp and v in0_bm are connected across load current sense resistor r50. a correction voltage is developed at the i out0 pin by sourcing idac0s current into resistor r40. r40 is kelvin connected to the point-of-load gnd in order to isolate v iout0 from ground bounce due to load current changes. v iout0 is replicated at v out0 by an on-chip, unity-gain voltage buffer. v out0 is then connected to the feedback node of the power supply through resistor r30. the feedback node can be isolated from the dacs correction voltage by placing the v out0 pin in high-impedance mode. since the gpio_cfg pin is pulled-up to v dd , the ltc2970s gpio_0 pin will automatically hold the power supplys run/ss pin low after power-up until the i 2 c interface releases it. figure 1. typical ltc2970 application circuit for dc/dc converters with external feedback resistors out fb r40 r10 r20 r30 r50 0.1 f 0.1 f i ? i + 1/2 ltc2970 v in0_bm v in0_bp v in0_ap v dc0 + ? v out0 i out0 v in0_am alert scl i 2 c bus sda gpio_0 ref v in gnd gnd asel0 asel1 load v dd gpio_cfg dc/dc converter sgnd 29701 f01 run/ss in v in 8v to 15v 0.1 f
ltc2970/ltc2970-1 28 29701fb applicatio s i for atio wu u u 4-step resistor selection procedure for dc/dc converters with external feedback resistors the following 4-step procedure should be used to quickly calculate the resistor values shown for the typical applica- tion circuit shown in figure 1. 1. assume values for feedback resistor r20 and the nominal dc/dc converter output voltage v dc0,nom , and solve for r10. v dc0,nom is the desired output voltage of the dc/dc con- verter when the ltc2970s v out0 pin is in a high impedance state. v fb0 is the voltage at the converters feedback node when the loop is in regulation, and i fb0 is the feedback nodes input current. r rv virv fb dc nom fb fb 10 20 20 0 00 = ? ?? ? , (1) 2. solve for the maximum value of r30 that yields the maximum required dc/dc converter output voltage v dc0,max . when v out0 is at 0v, the output of the dc/dc converter is at its maximum voltage. note that the 10mv term cor- responds to the maximum offset voltage of the idac 1x voltage buffer. r rv mv vv fb dc max dc nom 30 20 10 ?? () ? ,, (2) 3. solve for the minimum value of r40 thats needed to yield the minimum required dc/dc converter output voltage v dc0,min . the dc/dc converter output voltage will be a minimum when idac0 is at its full-scale current. in order to guarantee that r40 is large enough, assume that idac0s full-scale current is at the datasheet minimum of 236a. r vv r r vmv a dc nom dc min fb 40 30 20 10 236 ? () ?++ ,, (3) 4. re-calculate the minimum, nominal, and maximum dc/dc converter output voltages and the resulting mar- gining resolution. vv r r ir dc nom fb fb 0 1 20 10 20 , =?+ ? ? ? ? ? ? +? (4) vv r r ravm dc min dc nom fb 00 0 20 30 40 236 10 ,, ?? ??? vv () (5) vv r r vmv dc max dc nom fb 00 0 20 30 10 ,, +?? () (6) the margining resolution is bounded by: v r r ra res ?? 20 30 40 276 256 volts/dac lsb (7) margining dc/dc converters with a trim pin figure 2 illustrates a typical application circuit for margining the output voltage of a dc/dc converter with a trim pin. the ltc2970s v out0 pin connects directly to the trim pin through resistor r30 and the i out0 pin is terminated at the converter's point-of-load ground throught r40. resistors r30 and r40 give this application circuit two separate degrees of freedom so that the margin-up and margin-down percentages can be speci? ed independently of each other. following power-up, the ltc2970's v out0 pin defaults to a high-impedance state. if the soft-connect feature is used, figure 2. ltc2970 application circuit for dc/dc converters with a trim pin vo+ v sense? v sense+ r40 0.1 f 0.1 f trim 1/2 ltc2970 v out0 v in0_ap v dc0 + ? i out0 v in0_am alert scl i 2 c bus sda gpio_0 ref 12v in gnd asel0 asel1 load v dd gpio_cfg dc/dc converter vo? r30 29701 f02 on/off v in 8v to 15v 0.1 f
ltc2970/ltc2970-1 29 29701fb applicatio s i for atio wu u u the ltc2970 will automatically ? nd the idac code that most closely approximates the trim pin's open-circuit voltage before enabling v out0 . note: the relationship between v trim and the converter's output is typically non-invert- ing, so be sure to set the ltc2970's ch0_a_idac_pol bit to 1 in order to allow the voltage servo feature to function properly. dc/dc converters with a trim pin are usually margined high or low by connecting an external resistor between the trim pin and either the v sense+ or v senseC pin. the relationships between these resistors and the % change in the output voltage of the dc/dc converter are typically expressed as: r r r trim down trim down trim _ % = ? ? 50 (8) r rv v r trim up trim dc up ref up t _ % % = +? () ? ? 100 2 r rim up trim r % 50 ? ? ? ? ? ? ? ? (9) where r trim is the resistance looking into the trim pin, v ref is the trim pin's opern-circuit output voltage and v dc is the dc/dc converter's nominal output voltage. up % and down % denote the percentage change in the converter's output voltage when margining up or down respectively. 2-step resistor selection procedure for dc/dc converters with a trim pin the following two-step procedure should be used to calculate values for resistors r30 and r40 shown in figure 2. 1. solve for r30: rr trim down down 30 50 ?? ? ? ? ? ? ? ? % % (10) 2. solve for r40: r v a up down ref 40 1 236 + ? ? ? ? ? ? ? ? % % (11) tracking with the ltc2970-1 a typical ltc2970-1 tracking application circuit is shown in figure 3 (the sequence of events for tracking are described in sections 9 and 10 of the operation section). the gpio_0 and gpio_1 pins are tied directly to their respective dc/dc converter run/ss pins. since gpio_cfg is pulled-up to v dd , the ltc2970-1 will automatically hold off the dc/dc converters after power-up by asserting open drain outputs gpio_0 and gpio_1 low. n-channel fets q10/11 and diodes d10/11 form unidirectional range switches around resistors r30a/31a while gpio_cfg is high. these range switches allow the ltc2970-1s v out0 and v out1 pins to drive the converter outputs all the way to/from ground through resistors r30b/31b. when gpio_cfg pulls low, n-channel fets q10 and q11 will turn off. r30a/31a and r30b/31b then combine in series for normal margin operation. the 100k/0.1f low-pass ? lter in series with the gates of q10/11 minimizes charge injection into the feedback nodes of the dc/dc converters when gpio_cfg pulls low. figure 3. ltc2970-1 tracking application circuit 0.1 f 0.1 f ltc2970-1 i 2 c bus gpio_1 i out1 v out1 12v in gnd v dd gpio_cfg 10k 100k 29701 f03 alert scl sda in out dc/dc converter fb run/ss v in v dc1 r11 q10, q11: 2n7002 d10, d11: mmbd4448v *some details omitted for clarity r41 r21 r31a q11 d11 r31b gpio_0 i out0 v out0 in out dc/dc converter fb run/ss v in v dc0 r10 r40 r20 r30a q10 d10 r30b 8v to 15v 0.1 f
ltc2970/ltc2970-1 30 29701fb applicatio s i for atio wu u u 7-step procedure for calculating tracking application circuit resistor values, counter delay values, and terminal idac codes the following 7-step procedure should be used to calculate the resistor values, tracking counter delays, and terminal idac codes for the tracking application circuit shown in figure 3. 1. assume a value for r20 and solve for r21. v dc n ,nom is the output voltage of the dc/dc converter when the ltc2970s v out n pin is in a high impedance state. rr v v dc nom dc nom 21 20 1 0 =? , , (12) 2. solve for r10 and r11. r rn v v dc nom fb 1 2 1 n n n = ?
, (13) 3. solve for r40 and r41. for simplicity, this procedure assumes that r40 = r41. v dc n ,max and v dc n ,min are the maximum and minimum converter output margin voltages, respectively. the value of r40 = r41 is constrained by: rr v vv vv fb dc nom dc min dc max d 40 41 = ? ? () ? n nn n ,, , c c nom mv a n , () +

+ 110 236 (14) due to the forward drop of diodes d10 and d11 (0.8v max), the minimum value for r40 = r41 from expression (14) may result in small or even negative values of r30 and r31 in step 4. if this is the case, assume a minimum allowable value for r3 n b, and use the following expression to calculate the minimum value r40 = r41: rr v rb r rb r v fb 40 41 1 3 1 3 2 08 1 = ?+ +
++ n n n n n . 00 236 mv a (15) note: use the channel whose parameters yield the maxi- mum value for r40 = r41. 4. solve for r30b and r31b. solve for the upper limits of r30b and r31b and then determine which resistor value constrains the maximum value of the other resistor using equation 17. rb ravvmv v rr fb fb 3 4 236 0 8 10 1 1 1 n n n n n ???? () ?+ . 22 n
(16) rb r rb r 30 20 31 21 = (17) 5. solve for r30a and r31a. r30a and r31a are constrained by: ra r r r vv v dc max dc nom dc 3 2 1 2 1 n n n n nn +
? ? ,, nn n ,nom rb
? 3 (18)
ltc2970/ltc2970-1 31 29701fb applicatio s i for atio wu u u 6. solve for channel 1s tracking counter delay relative to channel 0, ch1_a_delay_track(). ch a delay track vv r dc nom dc nom 1 10 __ _ () ,, = ? () ? 331 21 141 b r a count r counts / () ? (19) note: v dc n ,nom ? is based on the ? nal values of r2 n and r1 n . if the result for ch1_a_delay_track() is less than 0, apply the unsigned result to the ch0_a_delay_track() register. 7. solve for the idac0 and idac1 terminal tracking codes, ch n _a_idac_track[7:0]. ch a idac track v alsbr l fb n n n __ _ [:] / ( 70 255 14 = ? ? s sb s ?) (20) note: this formula assumes that the ch n _a_idac_pol bit is set to 0. margining application circuit design example consider the ltc2970 application circuit shown in figure 1. channel 0 is a dc/dc converter whose output needs to be varied between 3.63v and 1.62v. v fb0 = 0.8v and assume that i fb0 = 0a. 1. assume values for feedback resistor r20 and the nominal dc/dc converter output voltage v dc0,nom , and solve for r10. let v dc0,nom = 2.625v (the average of 3.63v and 1.62v) and assume that r20 = 10k . from equation 1: r rv virv kv fb dc nom fb fb 10 20 20 10 0 8 0 00 = ? ?? ? = ? , . ? 22 625 0 8 4 384 .. , vv ? =? let r10 = 4.37k (the nearest e192 series resistor value). 2. solve for the value of r30 that yields the maximum required dc/dc converter output voltage v dc0,max from equation 2: r rv mv vv k fb dc max dc nom 30 20 10 10 0 0 ?? () ? = ? ,, .. ? 8 810 3 63 2 625 7 861 vmv vv ? () ? = .. , ? let r30 = 7.68k . 3. solve for the value of r40 thats needed to yield the minimum required dc/dc converter output voltage v dc0,min . from equation 3: r vv r r v a dc nom dc min fb 40 30 20 236 2 625 ? () ?+ = ,, . v vv k k v a ? () ?+ = 162 796 10 08 236 6 780 . . . , ? ? ? let r40 = 6.81k . 4. re-calculate the minimum, nominal, and maximum dc/dc converter output voltages and the resulting mar- gining resolution. from equations 4, 5, and 6: vv r r ir v dc nom fb fb 0 1 20 10 20 08 1 , . =?+ ? ? ? ? ? ? +? = ?+ 110 437 2 631 k k v ? ? . . ? ? ? ? ? ? = vv r r ar v dc min dc nom fb 00 0 20 30 236 40 ,, ltc2970/ltc2970-1 32 29701fb applicatio s i for atio wu u u vv r r vmv dc max dc nom fb 00 0 20 30 10 ,, >+?? () >+? ? () = vv k k vmv dc max 0 2 631 10 768 08 10 36 , . . .. ? ? 660v from equation 7, the margining resolution will be less than: v r r ra k k k res < ?? = ?? 20 30 40 276 256 10 768 665 ? ? ? . . 2276 256 933 a = . mv/lsb margining dc/dc converter with trim pin design example the output voltage of the dc/dc converter in figure 2 needs to be margined 10% about its nominal value. assume that r trim = 10.22k and v ref = 1.225v. 1. solve for r30 using equation 10: rr k trim down down 30 50 10 22 50 ? ? ? ? ? ? ? = ? % % . ? ? ? 1 10 10 40 880 ? ? ? ? ? ? = , ? let r30 = 39.2k . 2. solve for r40 using equations 11: r v a up down ref 40 1 236 1 10 10 + ? ? ? ? ? ? ? ? =+ ? ? ? ? % % ?? ? = . , 1 225 236 10 381 v a ? let r40 = 10.5k . tracking application circuit design example consider the ltc2970-1 application circuit shown in figure 3. channel 0 is a 1.8v dc/dc converter while channel 1 is a 2.5v switching power supply. both converters have a feedback node voltage of 0.8v and need to track on and off coincidentally. in addition, a margin range of +5% and C10% is required for each supply. 1. assume a value for r20 and solve for r21. let r20 = 5,970 . from equation 12: rr v v v v dc nom dc nom 21 20 5 970 25 18 8 1 0 =? = ? = , , , . . , ? 2292 ? let r21 = 8,250 (the nearest e192 series resistor value). 2. solve for r10 and r11. from equation 13: r r v v v v dc nom fb 10 20 1 5 970 18 08 0 0 = ? ? ? ? ? ? ? = ? , , . . ? 11 4 776 ? ? ? ? ? ? = , ? r r v v v v dc nom fb 11 21 1 8 250 25 08 1 1 = ? ? ? ? ? ? ? = ? , , . . ? 11 3 882 ? ? ? ? ? ? = , ? let r10 = 4,750 and r11 = 3,880 . 3. solve for r40 and r41. assume that r40 = r41. rr v vv vv fb dc nom dc min dc max d 40 41 = ? ? () ? ,, , c c nom mv a v n , . (.) ( () + ? ? ? ? ? ? ? ? + = ? ? 110 236 08 109 1 105 1 110 236 10 212 .) , ? + ? ? ? ? ? ? + = mv a ? let r40 = r41 = 10.5k
ltc2970/ltc2970-1 33 29701fb applicatio s i for atio wu u u 4. solve for r30b and r31b. rb ravvmv v rr fb fb 30 40 236 0 8 10 1 10 1 0 0 ???? () ?+ . 220 10 5 236 0 8 0 8 10 08 ? ? ? ? ? ? = ? ??? (. . . ) . k avvmv v ? ? ?+ ? ? ? ? ? ? = 1 4 750 1 5 970 2 870 ,, , ?? ? rb ravvmv v rr fb fb 31 41 236 0 8 10 1 11 1 1 1 ???? () ?+ . 221 10 5 236 0 8 0 8 10 08 ? ? ? ? ? ? = ? ??? (. . . ) . k avvmv v ? ? ?+ ? ? ? ? ? ? = 1 3 880 1 8 250 2 863 ,, , ?? ? for coincident tracking to occur equation 17 also must be satis? ed: rb r rb r 30 20 31 21 = =?= ? = rb rb r r 30 31 21 20 2 863 8 250 5 970 2 078 , , ,, ? ? ?? ? = ?= ? = rb rb r r 31 30 20 21 2 870 5 970 8 250 3 957 , , ,, ? ? ?? ? let r30b = 2,100 and r31b = 2,890 . 5. solve for r30a and r31a. referring to equation 18: ra r r r vv v dc max dc nom dc 30 20 1 20 10 00 + ? ? ? ? ? ? ? ? ,, 00 30 5 970 1 5 970 4 750 , , , , nom rb ? ? ? ? ? ? ?= + ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ?= 105 1 1 2 100 50 806 . ,, ?? ra r r r vv v dc max dc nom dc 31 21 1 21 11 11 + ? ? ? ? ? ? ? ? ,, 11 31 8 250 1 8 250 3 880 , , , , nom rb ? ? ? ? ? ? ?= + ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ?= 105 1 1 2 890 49 888 . ,, ?? let r30a = 49.9k and r31a = 48.7k . 6. solve for channel 1s tracking counter delay relative to channel 0, ch1_a_delay_track(). first, recalculate the values of v dc n ,nom based on the ? nal values of r1 n and r2 n : vv r r ir v dc nom fb fb 0 1 20 10 20 08 1 , . =?+ ? ? ? ? ? ? +? = ? ++ ? ? ? ? ? ? += 5 970 4 750 0 1 805 , , . ? ? v vv dc nom 1 08 1 8 250 3 880 0 2 501 , . , , . =?+ ? ? ? ? ? ? += ? ? vv next, apply equation 19: ch a delay track vv r dc nom dc nom 1 10 __ _ () ,, = ? () ? 331 21 141 2 501 1 805 2 890 b r a count r vv / .. , ? = ? () ? ? 88 250 1105 23 , /. ? ? a count k counts ? =
ltc2970/ltc2970-1 34 29701fb q1 tp0610k out fb r10 r20 r sense 0.1 f 0.1 f i 2 c bus load dc/dc converter v in v ee gnd r20 r10 29701 f05 1/2 ltc2970 alert scl sda ref 12v in gnd asel0 asel1 v dd v in0_bp v in0_bm v in0_ap i out0 v in0_am 8v to 15v 0.1 f v out = v dd ? ( 1 + r30 r40 ) v in0_ap ?v in0_am ? ( ) 7. solve for the idac0 and idac1 terminal tracking codes, ch n _a_idac_track[7:0]. ch a idac ch a idac v a 070170 255 08 1 __ [:] __ [:] . == ? / /. lsb k ? = 10 5 179 ? figure 4 shows the dc/dc converter output voltages for this design example tracking-up and tracking-down. negative power supply application circuit figure 5 shows the ltc2970 controlling a negative power supply. the r30/r40 resistor divider translates the point of load voltage to the ltc2970s v in0_a inputs while the v in0_b inputs monitor the converters input current i ? r drop across resistor r sense . since the v dd pin voltage is monitored by the ltc2970, its tolerance can be ac- counted for when calculating the point of load voltage. transistor q1 allows the i out0 pin to force current into the converters feedback node without forward biasing the ltc2970s i out0 body diode. note that i out0 s output current defaults to 128 a after the ltc2970 comes out of power-on reset. 15-bit programmable power supply application circuit figure 6 illustrates how both servo channels of the ltc2970 can be con? gured to adjust a single dc/dc converter over a 15-bit dynamic range. r30 and r31 are sized to force 1 bit of overlap between the coarse (channel 0) and ? ne (channel 1) servo loops. one coarse servo iteration should be performed ? rst on channel 0 with idac1 programmed to mid-scale, and then channel 1 can be programmed to servo to the desired voltage. programmable reference application circuit figure 7 shows a ltc2970 con? gured as a program- mable reference that can span a 0v to 3.5v range with a resolution of 100v and an absolute accuracy of less than 0.5%. the two idacs are paralleled by terminating idac1s output resistor in the v out0 output and taking the output of the composite dac from v out1 . idac0 should servo once with idac1 set to mid-scale, and then idac1 can servo once, continuously, or trigger on drift to the desired target voltage. figure 4. tracking design example dc/dc converter output waveforms applicatio s i for atio wu u u figure 5. negative power supply application circuit figure 6. programmable power supply application circuit 0 0.3 0.9 1.2 1.5 2.7 29701 f04 0.6 5ms/div volts 1.8 2.1 2.4 v dc1 v dc0 out fb r40 r10 r20 r30 0.1 f 0.1 f i 2 c bus load dc/dc converter sgnd 29701 f06 r31 r31 r30 128 r41 = r40 run/ss in v in ltc2970 alert scl sda gpio_0 ref 12v in gnd gnd asel0 asel1 v dd gpio_cfg v out1 v in1_ap v in0_ap v in1_am v out0 i out0 r41 i out1 v in0_am c load + 8v to 15v 0.1 f
ltc2970/ltc2970-1 35 29701fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 12.7k 10 ? 0.1 f 22 f 0.1 f i 2 c bus 100 ? 29701 f07 ltc2970 alert scl sda ref 12v in gnd asel0 asel1 v dd i out0 v in1_ap v in0_ap v out1 i out1 v out0 v out + ? v in0_am v in1_am 8v to 15v 0.1 f figure 7. programmable reference application circuit ufd package 24-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1696) package descriptio u 4.00 0.10 (2 sides) 2.65 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.05 23 24 1 2 bottom view?exposed pad 3.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.30 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd24) qfn 0505 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.65 0.05 (2 sides) 3.65 0.05 (2 sides) 4.10 0.05 5.50 0.05 3.10 0.05 4.50 0.05 package outline typical applicatio u
ltc2970/ltc2970-1 36 29701fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt/lwi 0606 ? printed in usa related parts part number description comments ltc2920-1/ltc2920-2 single/dual power supply margining controllers symmetric/asymmetric high and low voltage margining ltc2921/ltc2922 power supply trackers with input monitors 3 (ltc2921) or 5 (ltc2922) remote sense switches ltc2923 power supply tracking controller up to 3 supplies ltc2924 quad power supply sequencer voltage monitoring and sequence error detection and reporting ltc2925 multiple power supply tracking controller power good timer, remote sense switch ltc2926 mosfet controller power supply tracker up to 3 modules ltc2927 single power supply tracker point of load applications typical applicatio u out fb 0.1 f 0.1 f i? i+ i 2 c bus smbus compatible load dc/dc converter 0 sgnd 10k 29701 ta01 run/ss in v in ltc2970 alert scl sda gpio_0 rgnd ref 12v in gnd pgnd out fb i? i+ load dc/dc converter 1 sgnd run/ss in v in pgnd asel0 asel1 v dd gpio_cfg v in0_bm v in0_bp v in0_ap v out0 i out0 v in0_am gpio_1 v in1_bm v in1_bp v in1_ap v out1 i out1 v in1_am () r50 r30 r20 r10 r40 r51 r31 r21 r11 r41 8v to 15v 0.1 f 10 9 20 17 18 19 4 3 11 1 14 2 16 8 7 12 5 13 6 15 23 24 21 22 25 figure 8. typical ltc2970 application circuit for dc/dc converters with external feedback resistors

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